郭明錤｜Ming-Chi Kuo engagement report

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• Jun 28, 20263.9x their median

  The memory supply-demand gap will keep widening through 2027. That is the real reason Apple is lobbying the White House to keep CXMT off the Entity List. ▌Start with my latest industry checks: The pressure on Apple has shifted from soaring memory costs to a widening supply gap. 1. Of the memory capacity allocated to consumer electronics in 2026, an estimated 15–20% is expected to shift to data centers in 2027, and that share could grow. 2. Due to tight memory (LPDDR) supply, Apple's actual pull-in volume of A20 chips in 2H26–1Q27 could be 10–20% below its original target (though part of that may reflect Apple’s own overbooking). ▌CXMT states in its IPO prospectus that its capacity is far below domestic demand. Given the persistent global memory imbalance, even if Apple’s lobbying succeeds and it buys DRAM from CXMT, that would not materially lower costs or fill the supply gap. Still, with the imbalance widening, Apple has every reason to secure an additional source. ▌This also explains why Apple is being more proactive this time than it was when it evaluated YMTC in 2022. YMTC was mainly about lowering NAND costs; CXMT is about managing DRAM supply risk. ▌Tim Cook is one of the few tech leaders who can still navigate both Washington and Beijing, so this is better handled before he steps down as CEO. Even if the effort goes nowhere, the media coverage can still leave the market with the impression that Apple tried but was constrained by U.S. policy. That may help ease frustration over price hikes and longer delivery times.

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• Jun 26, 20263.6x their median

  iOS 27 will bring tighter system-level integration with Apple Intelligence. My latest industry checks suggest Apple's lower-end 1H27 iPhones, powered by the A20 chip, will move to 9GB DRAM (1.5GB × 6 dies), up from 8GB (2GB × 4 dies) in the current A19 models, to keep the system running smoothly under AI workloads. The three new high-end 2H26 models powered by the A20 Pro chip (the foldable and two 18 Pro models) will remain unchanged at 12GB (1.5GB × 8 dies).

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• Jun 28, 20263.3x their median

  2027 年記憶體供需缺口將持續擴大，這才是 Apple 遊說白宮「避免長鑫存儲未來被列入實體清單」的真相 ▌先講我最新的產業調查：Apple 面對的壓力，已從記憶體成本大增，升級到供需缺口持續擴大。 1. 2026 年用於消費電子的記憶體產能中，預計 15–20% 將於 2027 年轉供資料中心，且後續不排除繼續擴大。 2. 受記憶體（LPDDR）供應緊張影響，Apple 在 2H26–1Q27 對 A20 處理器的實際拉貨量，可能比原目標少 10–20%（不過，這也可能部分是 Apple over-booking 的結果）。 ▌長鑫在招股書中提到，該公司的產能遠低於國內需求；加上全球記憶體供需持續失衡，因此即便 Apple 遊說成功並向長鑫採購 DRAM，也不會顯著降低成本與改善供需缺口。但在供需失衡持續擴大下，Apple 仍有必要爭取新的供應來源。 ▌這也解釋為何 Apple 這次會比 2022 年評估長江存儲更積極。當年的長江，是提供改善 NAND 成本的選項；而這次的長鑫，則是管理 DRAM 供需失衡風險的選項。 ▌Tim Cook 是少數能同時與美中政府維持良好關係的科技領袖，故此事最好趕在他卸任 CEO 前完成。即便最終未果，透過媒體披露後，也能讓市場留下「Apple 已盡力、無奈仍受限於美方政策」的印象，或能緩和市場對漲價與交期拉長的不滿。

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• Jun 11, 20262.9x their median

  Key takeaways on TSMC's next-generation advanced packaging, CoPoS (publicly available technical details omitted): 1. CoPoS is currently expected to enter mass production in 2H28. It is designed to improve the economics of ultra-large packages above the 9.5x reticle-size class, with NVIDIA’s Feynman AI chip a potential first adopter. 2. According to industry checks, glass is used in two distinct places (dimensions in mm): → 310 x 310 temporary glass carriers → 250 x 250 (pilot) / 510 x 515 (mass production) glass panels, processed and later cut into individual glass core substrates 3. The glass core substrate is essentially a three-layer structure: a glass core sandwiched between ABF (ABF-GCP) build-up layers on both sides. The widely discussed glass processing challenges, such as TGV formation and copper filling / metallization, are tied to this part of the stack. 4. Common misconceptions about CoPoS: → ❌ Misconception 1: CoPoS uses a glass interposer. ⭕️ Correction: The glass is not an interposer. The interconnect role is instead handled by the chip-side RDL, plus the TGV/Cu interconnects and ABF build-up layers in the glass-core substrate stack. → ❌ Misconception 2: Glass replaces ABF. ⭕️ Correction: As the substrate architecture above shows, glass and ABF coexist. → ❌ Misconception 3: Chips sit directly on glass. ⭕️ Correction: Chips are attached to the ABF build-up surface of the glass core substrate. 5. CoPoS should extend and reinforce TSMC’s leadership in advanced packaging, potentially giving that advantage visibility through around 2032.

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• Jun 18, 20262.5x their median

  重點解讀台積電的玻璃核心載板投影片 台積電在 6 月 11 日的日本 JPCA Show 2026，進行主題為「AIの進化に不可欠な先端パッケージング技術」的簡報，該份簡報約40頁，當中某張標題為「Glass Substrate Development for CoWoS」的投影片流出，引發廣泛關注。 以下是對該投影片（見附圖）的重點解讀，能網路科普查到的技術細節就不多說了，要注意的是投影片上的 COP 不是 Chip-on-Package 的縮寫，而是 Coplanarity、也就是平整度 / 共面度。 ▌重點結論： 1. 台積電正式宣布與 Ibiden 以及群創合作，開發玻璃核心載板（glass core substrate），結構為玻璃上下各黏合 ABF 的三層結構設計，該技術就是用於 CoPoS 的 oS。 2. 市場低估玻璃核心載板的重要性，該技術對台積電是「must have」，意即 CoPoS 中，oS 的重要性高於 CoP，這也是該技術進行測試時，先搭配既有的 CoW 而非 CoP 的原因。 3. 玻璃核心載板單價較既有 ABF 載板高出數倍，群創加工的玻璃單價非常高，為最核心的材料。除 Nvidia 外，目前已有兩家美系客戶同樣表達高度興趣。 ▌與本投影片相關的產業調查： 1. 本投影片提及的玻璃核心載板由 250x250mm 切割而來，ABF 增層主要採用 Ajinomoto 的 GL107 並混搭 ABF-GCP，以 2027–2028 主流 AI 晶片 ABF 規格的 24-28 層進行測試 2. 台積電實驗時的 CoW 是測試載具（test vehicle），足以驗證採用複合材料時最具挑戰性的機械結構問題。測試結果良好意味著台積電、Ibiden 與群創已合作突破關鍵技術瓶頸。 3. 目前是由 Ibiden 負責切割 250x250mm 的玻璃核心載板。待 2H27 採用 510x515mm 做量產前模擬時，若 Ibiden 仍想降低生產複雜性以維持超高毛利率，可能會改交由更熟悉玻璃特性的群創切割。 ▌流出的投影片內容是將 CoPoS 中的 oS、也就是玻璃核心載板（投影片中的 glass-SBT）與 CoW 搭配的技術驗證結果，這是為解決該投影片前一頁所提到的「Substrate mechanical and electrical Dilemma」，而這顯著凸顯了 CoPoS 中 oS 的重要性。 1. CoPoS 中，CoP 要解決的是生產效率 / 切割經濟性的問題，這與成本與售價有關；而 oS 要解決的是翹曲與耐用性問題，這牽涉到能否做出晶片，以及晶片能否運作。 2. CoP 與 oS 兩者整合相得益彰，但展望未來數年，兩者的技術定位還是有些差異。CoP 是可選的絕佳優化選項（very-nice-to-have），沒有它的代價就是晶片更貴；但 oS 是必需品（must-have）， 沒有它可能連能否做出可用晶片都是問題。 3. 比較定位差異不是為了捧 oS 貶 CoP，這牽涉到客戶願意為哪個技術環節付錢的現實問題，細節下面分析。 ▌投影片中含金量最高的是電源完整性（power integrity；PI）改善，這對客戶意義重大，這也代表玻璃核心載板生產穩定後，台積電獲利能力與競爭優勢可望同步提升。 1. 技術說明：玻璃核心載板薄 → TGV（through glass via）垂直導通路徑短 → 導通路徑電阻（R）跟迴路電感（L）同降 → PI 改善 2. 對客戶意義重大原因：PI 改善 → 供電更穩 → 釋出功率餘裕（power headroom）→ 可整合更多電晶體、或拉高運作時脈 → AI 晶片算力提升 3. 對客戶而言，生產效率是台積電的基本責任，客戶不會為此多付錢；但 AI 算力提升能直接轉化為客戶的競爭力與獲利，故客戶願意為此買單。這也是 Nvidia 積極看待玻璃核心載板的原因。 4. 對台積電而言，玻璃核心載板可提升良率並降低成本，同時提高 AI 晶片的算力與售價，既是降本工具，也是漲價籌碼，對獲利與競爭力都是加分。 5. 目前載板成本佔 AI 晶片 BOM 約低個位數，封裝良率造成的損失約載板成本的 5-10 倍，故即便未來玻璃核心載板成本高於目前的數倍以上，但佔 BOM 比重仍低，且可改善封裝良率造成的損失，故預期玻璃核心載板的高單價不會影響客戶採用意願。 ▌簡報後的問答環節，有聽眾提問關於玻璃核心載板的 TGV 細節，台積電當場拒絕回答，因為玻璃核心載板的關鍵技術就是 TGV，核心 know-how 目前掌握在台積電與群創手中。相較下，另一個提問者的問題是關於 IVR、eDTC、與 LSI 的整合，台積電就回答了不少。 ▌根據產業調查，若一切順利，台積電的目標是在 4Q28-1Q29 開始量產玻璃核心載板，以符合 Nvidia AI 晶片迭代節奏。順帶一提，許多人在傳的 Ibiden 的法說投影片，上面將玻璃核心載板時程列為 CY30，我對此的解讀是：對外向來保守謹慎的 Ibiden 將玻璃核心載板正式列為發展路線，這更確定了該技術長期趨勢。但從 Ibiden 投影片的其他細節與市場資訊不完全一致來看，例如 reticle 時程與台積電公開宣稱的差約一個世代、Rubin Ultra 載板尺寸明顯大於其在 CY26-27 標示的 90x90 等，這說明了在預測未來時，需隨時多方交叉驗證。

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• Jun 11, 20262.4x their median

  關於台積電的次世代先進封裝 CoPoS 的幾個關鍵（省略可查詢到的技術細節）： 1. 預計 2H28 量產，目標提升 9.5 倍光罩尺寸以上的封裝之量產經濟性，Nvidia 的 AI 晶片 Feynman 可能將首度採用。 2. 根據產業調查，兩個不同的地方會用到玻璃（尺寸 mm）： → 310 x 310 的臨時玻璃載具（glass carrier） → 250 x 250（測試）/ 510 x 515（量產）的玻璃面板，加工後切割為玻璃核心載板（glass core substrate） 3. 玻璃核心載板的架構主要分成三層：玻璃作為核心層，上下以 ABF（ABF-GCP）增層包覆。玻璃加工的挑戰，像是TGV（through glass via）、填銅 / 金屬化（metallization）等，指的都是這個階段。 4. CoPoS 常見的錯誤論述： → ❌ 錯誤 1：採用玻璃中介層（interposer）。⭕️ 應修正為：玻璃非中介層，其互連角色由晶片側 RDL 與玻璃核心載板側 TGV / ABF 增層分別承接。 → ❌ 錯誤 2：玻璃取代 ABF。⭕️ 應修正為：如前述的玻璃核心載板架構，玻璃與 ABF 並存。 → ❌ 錯誤 3：晶片放在玻璃上。⭕️ 應修正為：晶片貼附於玻璃核心載板的 ABF 增層表面。 5. CoPoS 將延續並強化台積電先進封裝的優勢，預期讓該優勢能見度可達約2032年。

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• Jun 29, 20252.3x their median

  Apple Vision Series and Smart Glasses Roadmap (2025–2028): Smart Glasses Set to Drive the Next Wave in Consumer Electronics Full story: https://t.co/41Moxlj1Ai https://t.co/U2nQhBmEYg

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• Jun 22, 20262.0x their median

  Contrary to recent market rumors, my latest industry checks indicate that Google currently has no concrete plan to procure memory chips from CXMT.

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• Jun 18, 20261.9x their median

  Breaking down TSMC's glass core substrate slide On June 11, at JPCA Show 2026 in Japan, TSMC gave a roughly 40-slide presentation titled "Advanced Packaging Technology Essential to the Evolution of AI" (AIの進化に不可欠な先端パッケージング技術). One slide from the deck, titled "Glass Substrate Development for CoWoS," has since leaked online and widespread attention. Here's a closer read of that slide (see attached image). I'll skip the technical background that is already widely available. One thing to flag: the "COP" on the slide does not stand for Chip-on-Package. It means Coplanarity. ▌ Key conclusions: 1. TSMC has officially announced a partnership with Ibiden and Innolux to develop a glass core substrate. The structure is a three-layer design, a glass core sandwiched between two ABF build-up layers. This is the "oS" in CoPoS. 2. The market underestimates how important the glass core substrate is. It's a must-have capability for TSMC. In other words, within CoPoS the "oS" matters more than the "CoP", which is also why, when it was tested, it was paired with the existing CoW rather than with CoP. 3. The glass core substrate costs several times more per unit than existing ABF substrates. The glass processed by Innolux is very expensive per unit and is the single most critical material. Besides Nvidia, two US-based customers have also expressed strong interest. ▌ Industry checks tied to this slide: 1. The glass core substrate shown on the slide is cut from a full-size 250×250mm one. The ABF build-up layers mainly use Ajinomoto's GL107, mixed with ABF-GCP, and were tested at 24–28 layers, which is the mainstream ABF spec for AI chips in 2027–2028. 2. The CoW used in TSMC's experiment is a test vehicle. It is sufficient to validate the most challenging mechanical-structure issues that arise when working with composite materials. Good results mean TSMC, Ibiden, and Innolux have together broken through the critical technical bottleneck. 3. Ibiden currently handles cutting the 250×250mm glass core substrate. When the 510×515mm format is used for pre-mass-production simulation in 2H27, if Ibiden still wants to reduce production complexity to protect its ultra-high gross margins, it may hand the cutting over to Innolux, which is more familiar with the properties of glass. ▌ The leaked slide shows the validation results of pairing CoW with the "oS" in CoPoS, i.e., the glass core substrate (labeled "glass-SBT" on the slide). This addresses the "Substrate mechanical and electrical Dilemma" raised on the previous slide, and it strongly underscores how important the "oS" is within CoPoS. 1. Within CoPoS, what CoP solves is production efficiency / cutting economics, which ties to cost and price. What the oS solves is warpage and durability, which determines whether the chip can be made at all, and whether it can work. 2. CoP and oS complement each other well when integrated, but looking out over the next few years their technical roles still differ. CoP is a very-nice-to-have optimization, and going without it simply means a more expensive chip. But the oS is a must-have. Without it, even being able to make a usable chip is in doubt. 3. Comparing their roles isn't about elevating oS at the expense of CoP. It comes down to the practical question of which technical piece customers are willing to pay for. Details below. ▌ The real gold here is the power integrity (PI) improvement shown on the slide. This matters a great deal to customers, and it means that once glass core substrate production stabilizes, TSMC's profitability and competitive edge should rise in tandem. 1. How it works: the glass core substrate is thin → the vertical conduction path through TGV (through-glass vias) is short → conduction-path resistance (R) and loop inductance (L) both drop → PI improves. 2. Why it matters to customers: better PI → more stable power delivery → frees up power headroom → room to integrate more transistors, or to push clock speeds higher → more AI compute. 3. For customers, production efficiency is TSMC's basic responsibility, so they won't pay extra for it. But gains in AI compute translate directly into the customer's own competitiveness and profit, so customers are willing to pay for that. This is why Nvidia is so positive on the glass core substrate. 4. For TSMC, the glass core substrate raises yield and lowers cost while also boosting both the compute and the selling price of AI chips. It's both a cost-cutting tool and a pricing lever, a plus for profitability and competitiveness alike. 5. Substrate cost currently accounts for a low single-digit percentage of an AI chip's BOM, while losses from packaging yield run roughly 5–10× the substrate cost. So even if the glass core substrate ends up costing several times more than today's, its share of the BOM stays low, and it can cut the losses from packaging yield. The high unit price is therefore not expected to dampen customers' willingness to adopt it. ▌ In the Q&A after the presentation, an audience member asked about TGV details for the glass core substrate. TSMC declined to answer on the spot, because TGV is the key technology behind the glass core substrate, and the core know-how currently sits with TSMC and Innolux. By contrast, when another attendee asked about integrating IVR, eDTC, and LSI, TSMC answered at length. ▌ According to industry checks, if all goes well, TSMC is aiming to start mass production of the glass core substrate in 4Q28–1Q29, to match the cadence of Nvidia's AI chip iterations. As a side note: the Ibiden earnings presentation slide that many people have been circulating lists the glass core substrate timeline as CY30. My read is this: Ibiden, which has always been conservative and cautious in public, has now formally put the glass core substrate on its roadmap, which further confirms the long-term trend for this technology. That said, some other details on Ibiden's slide don't fully line up with what's known in the market. For example, its reticle timeline is off from TSMC's public claims by about a generation, and the Rubin Ultra substrate size is clearly larger than the 90×90 it marked for CY26–27. It's a reminder to always cross-check across multiple sources when forecasting the future.

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• Aug 10, 20261.9x their median

  市場近期傳聞，台積電因 DRAM 供應緊張，囤積約 10 億美元的 Apple 2nm 處理器半成品（傳聞稱為處理器晶圓）無法封裝，並以台積電 2Q26 法說提到「庫存天數增加主因是 2nm 量產爬坡」作為佐證。 我的產業調查顯示，Apple 今年的硬體出貨量確實因記憶體短缺而下調，但 Apple 在台積電的處理器訂單，會在至少約 3 個月前依可取得的記憶體數量規劃生產，而不是讓台積電提前大量生產半成品。 這不代表台積電不會提前生產並囤積半成品；但若瓶頸不在台積電，這麼做並無實益，因此，Apple 也沒有太大理由額外付錢要求台積電這樣做。 換言之，記憶體供應緊張是真，但我的理解是，並沒有出現「台積電先囤積 10 億美元半成品，再苦等記憶體到貨封裝」這種戲劇性變化。台積電與 Apple 都是全球執行力頂尖的企業，在供應鏈管理上，雙方緊密合作下也很難出現這種戲劇性的發展。 最後，憑公開資訊也能反思市場傳聞可能性。台積電在 2Q26 法說表示，庫存天數增加主要因 2nm 量產爬坡，但這裡的庫存不能直接視為由 Apple 處理器半成品造成，原因有三： 1. 台積電過往全新先進製程量產爬坡時，庫存天數通常也會增加，並非今年特有現象。 2. 台積電的庫存除半成品外，也包括製成品、原材料、物料與備品。 3. 今年 2nm 客戶不只有 Apple，還包括其他 IC 設計客戶（如 AMD 與聯發科）。

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